1. Field of the Invention
The present invention relates to a signal production circuit for producing a control signal which is used in a driving control circuit for driving and controlling a display panel, e.g., a flat panel, used in a wide range of applications such as an AV (audio vidual) apparatus and an OA (office automation) apparatus.
2. Description of the Related Art
In recent years, flat displays are replacing CRTs as next generation displays. Flat displays include a passive type liquid crystal display device which is used for a low-end product, and an active matrix type liquid crystal display device, an EL (electro-luminescent) display, a plasma display, etc., which are used for a high-end product. The active matrix type liquid crystal display device uses a 3-terminal element, e.g., a TFT (thin film transistor), or a 2-terminal element, e.g., an MIM (metal insulator metal) as a switching element. Typically, these flat displays use a display device having a matrix electrode structure, and are driven by a linear sequential driving method.
Referring to FIG. 11, a conventional liquid crystal display device 201 having a pixel driving section will be described as an example of such displays.
The liquid crystal display device 201 includes a display panel 203, which includes a plurality of data electrode lines X1 to Xn and a plurality of scanning electrode lines Y1 to Ym crossing the data electrode lines X1 to Xn. A plurality of pixels 202 are provided between the data electrode lines X1 to Xn and the scanning electrode lines Y1 to Ym at the respective intersections thereof. The pixels 202 are serially connected and each have an active element, which can be a 2-terminal element, a 3-terminal element, or the like.
An external interface signal IN is provided from an external circuit (not shown) to a control section 206 of the liquid crystal display device 201. For example, referring to FIG. 12, the external interface signal IN includes a data signal DATA to be displayed on the pixel 202 in synchronization with a reference clock CLK and a data enable signal ENAB indicating whether the data signal DATA is to be displayed. The external interface signal IN further includes a horizontal synchronization signal LP which is asserted for each of the scanning electrode lines Yj (j=1 to m) and a vertical synchronization signal FP which is asserted for each frame.
The vertical synchronization signal FP is input at a constant cycle for a particular display device and at a stable timing. While the vertical synchronization signal FP may cause a flicker when it is slower than a specific value, when the vertical synchronization signal FP is faster than the specific value, the power consumption of the display may increase, and additional components may be required to provide a display control circuit capable of being operated at the faster speed. Therefore, circuit designers attempt to operate the display device at a minimum possible speed which does not cause a flicker.
The number of reference clock CLK pulses for one cycle of the horizontal synchronization signal LP varies depending on the specification of the external circuit (not shown) which generates the external interface signal IN, and is often difficult to limit to a single value. For example, when designing a driving and controlling circuit using a memory IC for storing the data signal such as those typically called DRAMs which requires refresh pulses, the number of clock pulses varies due to the difference in display resolution among different display devices, and is thus often difficult to limit to a single value.
The control section 206 produces control signals indicating the driving voltage or the timing of the data electrode lines Xi (i=1 to n) and the scanning electrode lines Yj (j=1 to m). The control signals are sent to a scanning electrode line driving circuit 204 and a data electrode line driving circuit 205.
Based on the control signals, the scanning electrode line driving circuit 204 sequentially selects the scanning electrode lines Yj and applies a predetermined voltage thereto. Similarly, the data electrode line driving circuit 205 applies a predetermined voltage to the data electrode lines X1 to Xn according to the display data for the pixels 202.
Referring to FIGS. 14A to 14E, a voltage applied to the pixel 202 provided at each intersection of the data electrode line Xi and the scanning electrode line Yj will be described.
As illustrated in FIG. 14A, the horizontal synchronization signal LP is applied for each scanning electrode line. A selected pixel period (a period of time for which the pixel is selected) is one time period corresponding to the scanning electrode line Yj, as illustrated in FIG. 14A. FIG. 14B illustrates an alternating signal M produced based on the signal illustrated in FIG. 14A. The alternating signal M is a signal alternating at a predetermined cycle, e.g., for each scanning electrode line.
During a non-selected period, as illustrated in FIG. 14C, the scanning electrode line driving circuit 204 applies a voltage V.sub.1 or V.sub.4 to the scanning electrode line Yj according to the alternating signal M. As illustrated in FIG. 14D, the data electrode line driving circuit 205 selects a voltage to be applied to a data electrode line Xi depending upon whether the pixel 202 located at the intersection of the currently selected scanning electrode line Yj and the data electrode line Xi is turned ON. For example, V.sub.0 or V.sub.2 is selected when the alternating signal M is at a high level, and V.sub.3 or V.sub.5 is selected when the alternating signal M is at a low level. Thus, a voltage applied to the pixel 202 located at the intersection of the currently selected scanning electrode line Yj and the data electrode line Xi varies within a range from the ground level GND to a voltage Vb during a non-selected period, as illustrated in FIG. 14E.
During a selected period, on the other hand, V.sub.5 or V.sub.0 is applied to the scanning electrode line Yj according to the alternating signal M, as illustrated in FIG. 14C. As a result, when the data signal DATA indicates "ON", -V.sub.0 or V.sub.0 is applied to the pixel 202, as illustrated in FIG. 14E, thereby turning ON the pixel 202. When the data signal DATA indicates "OFF", a -V.sub.2 or V.sub.2 is applied to the pixel 202, thereby turning OFF the pixel 202. Thus, using the scanning electrode line driving circuit 204 and the data electrode line driving circuit 205, the pixel 202 can be driven by a voltage averaging method.
In order to realize an improved driving operation, it has been proposed to drive the device while shifting the signal timing by a certain length of time as described in Japanese Laid-open Publication No. 5-7136. Japanese Laid-open Publication No. 59-123884, discusses the necessity to shift the signal timing.
For example, consider a situation where an FET (field effect transistor) is used in the scanning electrode line driving circuit 204 or in the data electrode line driving circuit 205 in a voltage selection circuit of a power supply section. Referring to FIG. 15, after a control signal is externally input to the FET, there is a period of about 1 .mu.s during which both of a Pch (P-channel) FET and an Nch (N-channel) FET are substantially ON before the signals are completely switched. A through current which may occur during such a period is problematic in terms of the reliability of the device and the power consumption reduction. This necessitates the shifting of the signal timing.
In view of this, a control signal for the Pch FET and another control signal for the Nch FET can be separately provided while shifting the respective input timings, as illustrated in FIG. 16, thereby solving the above-described problem.
Thus, it is desired to provide a method for producing an original control signal and another control signal whose timing is shifted from the original control signal by about 1 .mu.s, so as to avoid a period during which both of the signals are substantially ON in order to realize an improved driving.
Conventionally, there have been two types of methods for producing shifted control signals:
1) For example, Japanese Laid-open Publication No. 5-7136. Uses a quartz oscillator, or the like, to generate an additional reference clock signal whose time interval is precisely known, and produce a second control signal by shifting from the original control signal by a period of time corresponding to a certain number of the additional reference clock signal pulses.
2) Use a resistor and a capacitor so as to delay a control signal, whose waveform is shaped by a Schmitt trigger input type IC, thereby obtaining another control signal shifted from the original control signal by a certain length of time.
However, both methods increase the number of components required and are thus inappropriate when the display device design aims to reduce the device size.
In accordance with the second method, a combination of a resistor and a capacitor approximately dictates one delay time. However, when a circuit using the resistor/capacitor combination is mass-produced, the delay time may vary among different modules due to the variation among individual resistors and capacitors.
In accordance with the first method, the signal generated by the quartz oscillator, or the like, is not in synchronization with the horizontal synchronization signals LP. Therefore, the following problems may occur when such a method is applied to a display device.
When there is a variation in the timing of a control signal used for applying a driving voltage, which should always be in synchronization with the horizontal synchronization signals LP, such a variation results in a perceivable defect in the display quality such as a flicker or a noise.
When the first method is applied to a display device, the following problems may also occur.
As the frequency of the quartz oscillator, or the like, is reduced to reduce the power consumption of the device, the variation in the signal timing with respect to the horizontal synchronization signals LP may become more significant. Conversely, when the frequency of the quartz oscillator, or the like, is increased, the synchronization accuracy may be improved to such a level that there is no defect in the display quality, but the power consumption increases. Moreover, a high performance circuit component may be required for providing a logic circuit capable of operating at a high frequency for processing such a signal. Furthermore, this can be a source of noise (i.e., undesired radiation).
The reference clock CLK included in the external interface signal IN is a signal similar to that generated by the quartz oscillator, or the like. The reference clock CLK is used for inputting the data signal DATA to the display device, and is in synchronization with the horizontal synchronization signals LP. If this signal can be used like the signal generated by the quartz oscillator, or the like, of the first method, the defect in the display quality may be eliminated by using an existing signal without providing an additional circuit component.
Unfortunately, as described above, it is difficult to limit the frequency of the reference clock CLK to a single, constant value. The specification of the driving control circuit and/or the resolution of the display screen may vary among different display device models, and the specification of the external interface signal IN varies accordingly. Therefore, when this technique is used in different display models, the number of reference clocks CLK pulses for one horizontal period cannot be limited to a single, constant value. Of course, the number of reference clocks CLK pulses for one frame period cannot be limited to a single, constant value. Accordingly, the length of time of one reference clock CLK also varies among different models, and thus is indefinite.